Hardware Assisted Verification

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Hardware Assisted Verification

(Hardware Emulation)

  • In house Veloce Strato CS emulator

  • Simulation Acceleration / in-circuit emulation

  • Software

  • Hardware co-emulation

  • Expertise in UVM, SystemVerilog, SystemC, embedded software, and co-debugging.

  • Experience in high speed interfaces test

  • Dedicated emulation lab with 24/7 access and remote debug infrastructure

  • Support for verification all stages

    Design spec review, Vplan creation, Test strategy development, Test environment creation, Testbench creation based on modern ,languages such as SV, SVA, UVM, SystemC, Metrics based verification – functional ,coverage development, Coverage Closure, Final test closure 

  • Vibe testing

  • AI based regression optimization

  • Proven success – including the emulation of OpenTitan, a high-complexity security project.

  • Delivered full RTL emulation of OpenTitan, a 100M+ gate open-source secure processor SoC.

  • Turnkey emulation solutions – from setup to execution to analysis.

Our solutions offerings cover the entire spectrum of pre-silicon verification and early software development, helping our clients accelerate time-to-market and reduce risk across complex SoC projects.

JumpStart Emulation free Trail

Try-on
  • Integration of the full SoC design including CPU, memory, interconnects, and peripherals.
  • Full system representation to target more realistic workloads across the system interfaces and perhipherals
  • Emulation of system traffic and interface protocols using Veloce’s VirtuaLAB and SpeedBridge technologies.
  • Exercise the design with Virtual and Physical targets
  • Running complex workloads across multiple interfaces to validate system coherency and robustness.
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Result

    1. Caught over 30% of post-simulation bugs in early customer projects.
    2. Ran 100+ system-level test scenarios per week, vs <10 on simulation.
    3. Verified complex interactions across 15+ interfaces (PCIe, USB, Ethernet, AXI) in a single emulated run.
    4. Early identification of system integration bugs (e.g., interconnect deadlocks, protocol violations).
    5. Verification under real-world software-driven traffic, reducing late-stage surprises.
    6.  Improved confidence in tape-out readiness through system-level stress testing.
    7. Detected rare deadlocks, coherency issues, and timing bugs seen only after 500M+ cycles.
    8. Cut time to reach system stability by 60–70% compared to traditional flows.
  • Stress the design with larger and more complex stimulaus
  • Test bench and environment in UVM/SystemVerilog, SystemC, C++
  • Minimal change to the testbench
  • Re-use code/functional coverage and assertions
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Result

    1. 10x to 100x faster execution compared to RTL simulation.
    2. Run 10 million+ cycles per test to expose deep functional bugs.
    3. Ability to run millions of cycles per test, exposing deeper corner cases.
    4. Reduction in simulation timeout and coverage gaps, improving overall verification quality.
    5. Reduced testbench resource usage by 50%, enabling better parallel job scaling.
  • Shift-left software bring-up and system integration
  • Run real firmware and software workloads
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Result

    1. Software readiness well before silicon availability – reducing bring-up time post-silicon.
    2.  Identification of HW/SW interaction issues early (e.g., MMU config bugs, interrupt handling faults).
    3.   Enabling parallel software and hardware development, reducing critical path bottlenecks.
    4. Reduced post-silicon bring-up from 12 weeks to <4 weeks.
    5. Ran full Linux boot in <10 minutes on emulation (vs non-bootable in simulation).
    6. Validated over 200 software test cases pre-silicon, including driver, memory, and I/O stack tests.
    7. Detected and fixed 20+ firmware bugs prior to silicon tape-out in a recent customer project.
    8. Improved HW/SW integration efficiency by 40–60%, enabling earlier design lock.

 At Inttegral, we specialize in cutting-edge emulation technologies designed to accelerate and secure the development of modern hardware and software systems. Our solutions empower engineering teams to simulate, validate, and optimize complex silicon architectures long before physical prototypes are built—reducing time-to-market and ensuring robust design integrity.

OpenTitan Project

We are honored to have been active contributors to OpenTitan, the world’s first open-source silicon Root of Trust (RoT) platform. OpenTitan is an Apache-2.0 licensed project, initiated by lowRISC in collaboration with Google, ETH Zurich, Nuvoton, Western Digital, Seagate, and others 

OpenTitan broke new ground: it achieved a full discrete silicon tape-out in June 2023, reached commercial-grade availability by early 2024, and entered production via fabrication with Nuvoton and integration in major platforms like Chromebooks. Its transparent, auditable design represents a pivotal shift in hardware-rooted security 

Through our emulation expertise, we supported OpenTitan’s development by:

  • Simulating secure boot sequences and lifecycle management

  • Emulating cryptographic modules and key handling

  • Accelerating verification across RTL, firmware, and system integration stages

Benefits of Veloce emulator

  • Robust environment – very few crashes

  • Deterministic test scenarios -> not possible to miss the issue

  • Faster compile time

Emulation Flow high level

  • The process begins with your RTL design (written in Verilog, SystemVerilog, or VHDL) or a gate-level netlist.
  • This is your hardware design’s functional description.
  • The first compiler stage translates the RTL into a Veloce Primitive Netlist.
  • This netlist uses special logic primitives understood by the Veloce emulation system.
  • It prepares the design for hardware mapping.
  • The primitive netlist is compiled further into a format compatible with Crystal SoC, the emulation fabric inside Veloce.
  • Crystal is Siemens’ custom FPGA-like architecture optimized for emulation.
  • The compiled design is then targeted to an AVB (Array of Veloce Boards).
  • The design is partitioned and mapped across the Crystal SoC hardware array.
  • Another compiler stage prepares the full binary image for deployment to the Veloce Module/Chassis (the physical emulation machine).
  • The compiled image is loaded onto the Veloce platform.
  • The system is now ready for hardware-accelerated emulation, enabling high-speed simulation, software validation, and debug.

High-Level Integration Flow (Customer-to-Emulation)

  • Sign NDA and agree on IP protection terms.
  • Define:
    • Scope of emulation (full-chip? block-level?)
    • Expected deliverables (waveforms, logs, test reports)
    • Timeline & test scenarios
  • RTL or gate-level netlist
  • Testbench or firmware (bare-metal, U-Boot, OS, etc.)
  • Clock/reset specs
  • Memory map and configuration
  • Constraints (timing, area, frequency)
  • Simulation models (if needed)
  • Any required 3rd-party IP or encrypted blocks

 

  • Validate RTL syntax, hierarchy, and compile-time correctness
  • Stub or replace un-emulatable parts (e.g. certain analog blocks)
  • Integrate transactors or BFM (Bus Functional Models), if needed
  • Add required Veloce-compatible wrappers (e.g., for clocks, resets)
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  • Step 1: Compile RTL → Veloce primitive netlist
  • Step 2: Map to Crystal SoC format
  • Step 3: Partition & compile to AVB and Veloce platform
  • Step 4: Load to Module/Chassis

Use Siemens’ tools like

  • Veloce compiler
  • Design Planner
  • Partitioning tools
  • Emulation Manager
  • Run customer’s testcases or your own regressions
  • Monitor with:
    • Waveform viewer (e.g., FSDB, VCD)
    • Debug probes / assertions
    • Log capture
  • Optionally use:
    • Virtual peripherals (UART, JTAG)
    • Co-modeling (for software integration)
    • ICE/Target HW interface if needed

Deliverables to customer:

  • Waveform traces
  • Log files / console output
  • Coverage reports (optional)
  • Debug snapshots
  • Performance stats

 

  • Weekly or milestone-based reports
  • Discuss issues found, debug logs
  • Help customer fix or recompile RTL if bugs found
  • Iterate quickly for new drops

Repeat / Regression Flow

  • Support updated RTL/testbench drops from customer
  • Re-run emulation
  • Add automation if recurring (CI/CD-style flow)

Optional: Security/Isolation Measures

  • Use dedicated project environments
  • Isolate customer data from other projects
  • Provide controlled remote access to waveform/debug interface